1. Field of Invention
The present invention relates generally to integrated circuits, and more particularly to dynamic random-access memories (DRAMs).
2. Description of Related Art
Networking companies are scrambling in a race to design and develop high performance network processing products for the terabit router market while reducing the cost to implement 10 giga-bits per second/OC192 and above optical carrier network interfaces. Terabit routers demand a fatter throughput of data packets for examining an incoming packet, retrieves a next hop location, and transfers the packet to destination. Memory chips serve as integral components in building a fast network infrastructure. As designers and manufactures attempt to increase the capacity in high-density memory chips, a redundancy memory scheme represents a significant portion in the overall finctionalities of a memory chip.
In a conventional memory, the design is typically rigid in which one redundancy column is dedicated for replacing a particular defective memory column. Such scheme may be too limiting if several memory columns fail, which occur more frequently with high-density memories and wide IO DRAMs. Accordingly, it is desirable to have a memory structure that employs intelligent and flexible column redundancy designs for increasing the overall operations in DRAMs.